Hardware that says no.
A hardware coprocessor that evaluates policy circuits — ALLOW or BLOCK — before any AI action reaches the host. No software can override it. The chip says no, and that's final.
“RLHF teaches an AI to prefer correct behavior. The BPU enforces boundaries in hardware. Software policies can be circumvented. Hardware gates cannot.”
[01] ARCHITECTURE
Three subsystems. Fixed pipeline.
Monomer Gates
Dedicated silicon units for each canonical operation. Each unit is a hardwired combinational circuit with no firmware.
Composition Router
Routes monomer calls according to composition laws: sequential, parallel, and conditional evaluation paths.
Verification Unit
Coherence verification unit. Certifies that every policy circuit meets formal correctness criteria before it is loaded into the BPU.
[02] THE NON-MASKABLE BLOCK
No software can override hardware.
Software Guardrails
RLHF, Constitutional AI, output filters — all operate in the same execution context as the AI model. A sufficiently capable model can find adversarial routes around these checks. If it runs as software on the same CPU, it can be disabled.
Hardware Enforcement
The BPU sits on the PCIe bus between the AI accelerator and the host I/O subsystem. A BLOCK terminates the PCIe transaction at the hardware level. No interrupt handler, no signal, no exception. The AI process never learns the block happened.
Threat Model
Protects against: compromised, jailbroken, or misaligned AI models. Does NOT protect against: compromised host OS or malicious human with physical access. Guards the boundary between AI actions and the systems they target.
[03] POLICY CIRCUITS
AI safety by physics, not psychology.
A Policy Circuit takes an action descriptor, evaluates it against certified constraints, and returns exactly ALLOW or BLOCK. Φc = 1 means every possible input maps deterministically to one of two terminal states.
Warehouse Robot
Zone boundaries, speed limits near humans, and restricted area enforcement. The robot physically cannot violate these constraints, regardless of what its AI model decides.
Delivery Drone
Altitude ceilings, no-fly zone geofencing, and automatic return-to-base on low battery. Hardware-enforced limits that no software update can bypass.
Surgical Robot Arm
Force limits and movement boundaries that cannot be overridden by any software. Critical zones enforce stricter constraints automatically.
[04] ROADMAP
From software to silicon
Phase 1 — Software
Policy circuits compile to Rust, JavaScript, and Python guardrail modules. Φ_c = 1 verified by the formal proof checker.
$ brikc compile --target rust policy.pcdPhase 2 — FPGA
Full BPU architecture on Xilinx Ultrascale+ FPGA. EVA Router and CMF Unit in synthesizable VHDL. Developer boards and server expansion cards.
Phase 3 — Silicon
Tape-out as a dedicated ASIC. ARM-style IP licensing model. Target: AI accelerator cards, server CPUs, edge AI SoCs.
Regulatory trajectory
Concept & software prototype
Now
ABS optional (1978)
FPGA validation
12–18 months
ABS standard equipment
Silicon target
24–36 months
ABS mandatory (2004)
[05] SPECIFICATIONS
Phase 1 is available now.
Policy circuits compile to Rust, JavaScript, and Python guardrails today. Free. Start writing policy circuits now — the silicon will catch up.